1. Field of the Invention
This invention relates to a semiconductor device and its manufacturing method, especially to an improvement of a breakdown voltage of a high voltage MOS (Metal Oxide Silicon) transistor for a level shifter used in a LCD (Liquid Crystal Display) driver and an EL (Electro Luminescence) driver.
2. Description of the Related Art
The semiconductor device of the prior art will be explained hereinafter by referring to a cross-sectional view of a LOCOS (Local Oxidation of Silicon) offset type high voltage MOS transistor shown in FIG. 13.
As shown in FIG. 13, a gate electrode 53 is formed through first and second gate insulating films 52A and 52B on a semiconductor layer of a first conductivity type (for example, a P type semiconductor substrate or a P type semiconductor layer, and a P type well region is used in this embodiment). An N+ type source region 54 is formed adjacent one end of the gate electrode 53 and an N− type drain region 56 is formed facing the source region 54 with a channel region 55 between them. Also, an N+ type drain region 57 is formed away from the other end of the gate electrode 53 and surrounded by the N− type drain region 56. A reference numeral 58 indicates a device isolation film.
The gate insulating film (the second gate insulating film 52B) is thicker than that of the normal voltage MOS transistor (for example, 10V). That is, the gate insulating film of the high voltage MOS transistor has a thickness of 120 nm, compared to the gate insulating film of the normal voltage MOS transistor with a thickness of 15 mn.
Additionally, the concentration of the electric field in this region is relieved because a LOCOS insulating film (the second gate insulating film 52B) is formed on the N− type drain region 56, improving the breakdown voltage.
Boron ion impurities for controlling a threshold voltage are implanted into an upper region of the P type well region 51 and thermally diffused underneath the channel region 55 (the shaded area in the channel region 55 in FIG. 13).
The impurity concentrations in the N− type drain region 56 and the semiconductor layer (P type well region 51) mainly determine the breakdown voltage of the transistor. Therefore, when the impurities are implanted into the channel region for controlling the threshold voltage, the breakdown voltage is reduced as the impurity concentration of the P type well region 51 increases.
Therefore, this invention is directed to providing a semiconductor device with an improved breakdown voltage and its manufacturing method.